Field
Embodiments of the present disclosure generally relate to methods and device structures which may be utilized in advanced patterning schemes. More specifically, embodiments described herein relate to three dimensional (3D) material modification for advanced processing methods.
Description of the Related Art
In response to an increased need for smaller electronic devices with denser circuits, devices with three dimensional (3D) structures have been developed. An example of such devices may include FinFETs having conductive fin-like structures that are raised vertically above a horizontally extending substrate. Conventional FinFETs may be formed on a substrate, such as a semiconducting substrate or silicon-on-insulator (SOI). The substrate may comprise a semiconducting substrate and an oxide layer disposed on the semiconducting substrate.
In light of the continued demand for continually smaller devices, various integration and advanced patterning schemes have been proposed. Examples of advanced applications include fin isolation, gate-all-around and 3D capping, among others. These 3D integration schemes generally demand precise processing capabilities which are operable at increasingly reduced technology nodes. For example, 3D hardmasks are often required to protect fin structures. However, various challenges arise in the manufacture of such features. Etch selectivity often limits the usefulness of many conventional hardmask formation processes and conventional processing schemes may lack the ability to be implemented efficiently and economically at advanced technology nodes.
Thus, what is needed are improved 3D processing methods and device structures.